MIPS instruction set - A highly abstract and simplified overview - To build up a datapath and construct a simple version of a processor - A more realistic. •Compiler can fill a single delay. • Rather than conditionally discard. single port Branch likely cancels delay slot if not taken MIPS I instruction set architecture made pipeline visible (delayed. Single delay slot impacts the critical path. Pipelining and Instruction Level Parallelism: 5 Steps of MIPS. (The most common example of this is the branch delay slot in MIPS processors. The instructions in the delay slots are always fetched. Branch: execute successor even if branch taken! Then branch target or continue. □ In 5-stages pipeline: 1 delay slot. Branch instruction. Example: Dual-port port vs. 5 Techniques for handling branches IF ID EX MEM WB • Stalling • Branch delay slots • Relies on programmer/compiler to fill • Depends on. The Branch Delay Slot • The location that follows a branch instruction is called the branch delay slot. (Example?) Example Delayed Branch. ) The discussion in section of Volume 3 of the Intel SW. . □ Idea: Branch happens after executing n subsequent instructions to branch instruction.